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| pre-production this is a product in the pre-production phase of development. device ramtron international corporation characterization is complete and ramtron does not expect to change the 1850 ramtron drive, colorado springs, co 80921 specifications. ramtron will issue a product change notice if any (800) 545-fram, (719) 481-7000 specification changes are made. http://www.ramtron.com rev. 2.0 feb. 2009 page 1 of 28 fm33256/fm3316 3v integrated processor companion with memory features high integration device replaces multiple parts ? serial nonvolatile memory ? real-time clock (rtc) with alarm ? low v dd detection drives reset ? watchdog window timer ? early power-fail warning/nmi ? 16-bit nonvolatile event counter ? serial number with write-lock for security ferroelectric nonvolatile ram ? 256kb and 16kb versions ? unlimited read/write endurance ? 45 year data retention ? nodelay? writes real-time clock/calendar ? backup current under 1 a ? seconds through centuries in bcd format ? tracks leap years through 2099 ? uses standard 32.768 khz crystal ? software calibration ? supports battery or capacitor backup processor companion ? active-low reset output for v dd and watchdog ? programmable low-v dd reset thresholds ? manual reset filtered and debounced ? programmable watchdog window timer ? nonvolatile event counter tracks system intrusions or other events ? comparator for power-fail interrupt or other use ? 64-bit programmable serial number with lock fast spi interface ? up to 16 mhz maximum bus frequency ? rtc, supervisor controlled via spi interface ? spi mode 0 & 3 (cpol, cpha=0,0 & 1,1) easy to use configurations ? operates from 2.7 to 3.6v ? small footprint ?green? 14-pin soic (-g) ? low operating current, 50 a standby current ? -40 c to +85 c operation ? underwriters laboratory (ul) recognized description the fm33256 and fm3316 are devices that integrate f-ram memory with the most commonly needed functions for processor-based systems. major features include nonvolatile memory, real-time clock, low-v dd reset, watchdog timer, nonvolatile event counter, lockable 64-bit serial number area, and general purpose comparator that can be used for a power-fail (nmi) interrupt or other purpose. the devices operate from 2.7 to 3.6v. each fm33xx provides nonvolatile ram available in memory capacity of 16kb and 256kb. fast write speed and unlimited endurance allow the memory to serve as extra ram or conventional nonvolatile storage. this memory is truly nonvolatile rather than battery backed. the real-time clock (rtc) provides time and date information in bcd format. it can be permanently powered from external backup voltage source, either a battery or a capacitor. the timekeeper uses a common external 32.768 khz crystal and provides a calibration mode that allows software adjustment of timekeeping accuracy. the processor companion includes commonly needed cpu support functions. supervisory functions include a reset output signal controlled by either a low v dd condition or a watchdog timeout. /rst goes active when v dd drops below a programmable threshold and remains active for 100 ms (max.) after v dd rises above the trip point. a programmable watchdog timer runs from 60 ms to 1.8 seconds. the timer may also be programmed for a delayed start, which functions as a window timer. the watchdog timer is optional, but if enabled it will assert the reset signal for 100 ms if not restarted by the host within the time window. a flag-bit indicates the source of the reset. a comparator on pfi compares an external input pin to the onboard 1.5v reference. this is useful for generating a power-fail interrupt (nmi) but can be used for any purpose. the family also includes a programmable 64-bit serial number that can be locked making it unalterable. additionally it offers an event counter that tracks the number of rising or falling edges detected on a dedicated input pin. the counter can be programmed to be non-volatile under v dd power or battery-backed using only v bak . if v bak is connected to a battery or capacitor, then events will be counted even in the absence of v dd .
fm33256/fm3316 spi companion w/ fram rev. 2.0 feb. 2009 page 2 of 28 pin configuration pin name function /cs chip select sck serial clock si serial data input so serial data output pfi power fail input pfo power fail output (nmi) cnt event counter input acs alarm/calibration/sqwave /rst reset input/output x1, x2 crystal connections vdd supply voltage vbak battery-backup supply vss ground pin descriptions pin name type pin description /cs input chip select: this active low input activates the device. when high, the device enters low- power standby mode, ignores the sck and si inputs, and the so output is tri-stated. when low, the device internally activates the sck signal. a falling edge on /cs must occur prior to every op-code. sck input serial clock: all i/o activity is synchronized to the serial clock. inputs are latched on the rising edge and outputs occur on the falling edge. since the device is static, the clock frequency may be any value between 0 and 16 mhz and may be interrupted at any time. si input serial input: all data is input to the device on this pin. the pin is sampled on the rising edge of sck and is ignored at other times. it should always be driven to a valid logic level to meet i dd specifications. the si pin may be connected to so for a single pin data interface. so output serial output: this is the data output pin. it is driven during a read and remains tri-stated at all other times. data transitions are driven on the falling edge of the serial clock. the so pin may be connected to si for a single pin data interface. cnt input event counter input: this input increments the counter when an edge is detected on this pin. the polarity is programmable and the counter value is nonvolatile or battery-backed, depending on the mode. this pin should be tied to ground if unused. acs output alarm/calibration/squarewave: this is an open-drain output that requires an external pullup resistor. in normal operation, this pin acts as the active-low alarm output. in calibration mode, a 512 hz square-wave is driven out. in squarewave mode, the user may select a frequency of 1, 512, 4096, or 32768 hz to be used as a continuous output. the squarewave mode is entered by clearing the al/sw and cal bits in register 18h. x1, x2 i/o 32.768 khz crystal connection. when using an external oscillator, apply the clock to x1 and a dc mid-level to x2 (see crystal type section for suggestions). /rst i/o reset: this active-low output is open drain with weak pull-up. it is also an input when used as a manual reset. this pin should be left floating if unused. pfi input early power-fail input: typically connected to an unregulated power supply to detect an early power failure. this pin must be tied to ground if unused. pfo output early power-fail output: this pin is the early power-fail output and is typically used to drive a microcontroller nmi pin. pfo drives low when the pfi voltage is <1.5v. vbak supply backup supply voltage: a 3v battery or a large value capacitor. if no backup supply is used, this pin should be tied to v ss and the vbc bit should be cleared. the trickle charger is ul recognized and ensures no excessive current when using a lithium battery. vdd supply supply voltage. vss supply ground vdd pfi acs sck pfo si rst vss x1 vba k cnt 1 2 3 4 5 6 7 14 13 12 11 10 9 8 x2 so cs fm33256/fm3316 spi companion w/ fram rev. 2.0 feb. 2009 page 3 of 28 figure 1. block diagram ordering information base configuration memory size operating voltage max. clock freq. reset thresholds ordering part number fm33256 256kb 2.7-3.6v 16 mhz 2.6v, 2.75, 2.9, 3.0v fm33256-g 256kb 2.7-3.6v 16 mhz 2.6v, 2.75, 2.9, 3.0v fm33256-gtr (tape&reel) fm3316 16kb 2.7-3.6v 16 mhz 2.6v, 2.75, 2.9, 3.0v fm3316-g 16kb 2.7-3.6v 16 mhz 2.6v, 2.75, 2.9, 3.0v fm3316-gtr (tape&reel) other memory configurations may be available. please contact the factory for more information. fram array spi interface sck si rst cs pfi vdd vbak rtc - + rtc re g isters cnt special function registers s/n x1 x2 lockout + - 1.5v watchdo g lv detect switched power 512hz/sqw rtc cal. battery backed nonvolatile so pfo acs alarm event counter alarm v sw nv/bb user programmable manual reset fm33256/fm3316 spi companion w/ fram rev. 2.0 feb. 2009 page 4 of 28 overview the fm33xx devices combine a serial nonvolatile ram with a real-time clock (rtc) and a processor companion. the companion is a highly integrated peripheral including a processor supervisor, analog comparator, a nonvolatile counter, and a serial number. the fm33xx integrates these complementary but distinct functions under a common interface in a single package. although monolithic, the product is organized as two logical devices. the first is a memory and the second is the companion which includes all the remaining functions. from the system perspective they appear to be two separate devices with unique op-codes on the serial bus. the memory is organized as a standalone nonvolatile spi memory using standard op-codes. the real-time clock and supervisor functions are accessed under their own op-codes. the clock and supervisor functions are controlled by 30 special function registers. the rtc/alarm and some control registers are maintained by the power source on the vbak pin, allowing them to operate from battery or backup capacitor power when v dd drops below a set threshold. each functional block is described below. memory operation the fm33xx products are available in memory sizes of 16kb and 256kb. the two devices are software compatible; that is, both versions use consistent two- byte addressing for the memory device. this makes both devices the same as its standalone memory counterparts, such as the fm25l16. memory is organized in bytes, for example the 256kb memory is 32,768 x 8. the memory is based on f-ram technology. therefore it can be treated as ram and is read or written at the speed of the spi bus with no delays for write operations. it also offers effectively unlimited write endurance unlike other nonvolatile memory technologies. the spi protocol is described on page 18. the memory array can be write-protected by software. two bits in the status register control the protection setting. based on the setting, the protected addresses cannot be written. the status register & write protection is described in more detail on page 20. processor companion in addition to nonvolatile ram, the fm33xx devices incorporate a real-time clock with alarm and highly integrated processor companion. the companion includes a low-v dd reset, a programmable watchdog timer, a 16-bit nonvolatile event counter, a comparator for early power-fail detection or other purposes, and a 64-bit serial number. processor supervisor supervisors provide a host processor two basic functions: detection of power supply fault conditions and a watchdog timer to escape a software lockup condition. both fm33xx devices have a reset pin (/rst) to drive a processor reset input during power faults, power-up, and software lockups. it is an open drain output with a weak internal pull-up to v dd . this allows other reset sources to be wire-or?d to the /rst pin. when v dd is above the programmed trip point, /rst output is pulled weakly to v dd . if v dd drops below the reset trip point voltage level (v tp ), the /rst pin will be driven low. it will remain low until v dd falls too low for circuit operation which is the v rst level. when v dd rises again above v tp , /rst continues to drive low for at least 50 ms (t rpu ) to ensure a robust system reset at a reliable v dd level. after t rpu has been met, the /rst pin will return to the weak high state. while /rst is asserted, serial bus activity is locked out even if a transaction occurred as v dd dropped below v tp . a memory operation started while v dd is above v tp will be completed internally. table 1 below shows how bits vtp(1:0) control the trip point of the low-v dd reset. they are located in register 18h, bits 0 and 1. the reset pin will drive low when v dd is below the selected v tp voltage, and the spi interface and f-ram array will be locked out. figure 2 illustrates the reset operation in response to a low v dd . table 1. vtp setting vtp1 vtp0 2.6v 0 0 2.75v 0 1 2.9v 1 0 3.0v 1 1 vdd vtp trpu rst figure 2. low v dd reset a watchdog timer can also be used to drive an active reset signal. the watchdog is a free-running programmable timer. the timeout period can be software programmed from 60 ms to 1.8 seconds in fm33256/fm3316 spi companion w/ fram rev. 2.0 feb. 2009 page 5 of 28 60 ms increments via a 5-bit nonvolatile setting (register 0ch). figure 3. watchdog timer the watchdog also incorporates a window timer feature that allows a delayed start. the starting time and ending time defines the window and each may be set independently. the starting time has 25 ms resolution and 0 ms to 775 ms range. figure 4. window timer the watchdog endtime value is located in register 0ch, bits 4-0, the watchdog enable is bit 7. the watchdog is restarted by writing the pattern 1010b to the lower nibble of register 0ah. writing the correct pattern will also cause the timer to load new timeout values. writing other patterns to this address will not affect its operation. note the watchdog timer is free- running. prior to enabling it, users should restart the timer as described above. this assures that the full timeout is provided immediately after enabling. the watchdog is disabled when v dd drops below v tp . note setting the endtime timeout setting to all zeroes (00000b) disables the timer to save power. the listing below summarizes the watchdog bits. watchdog starttime wdst4-0 0bh, bits 4-0 watchdog endtime wdet4-0 0ch, bits 4-0 watchdog enable wde 0ch, bit 7 watchdog restart wr3-0 0ah, bits 3-0 watchdog flags ewdf, 09h, bit 7 lwdf 09h, bit 6 the programmed starttime value is a guaranteed maximum time while the endtime value is a guaranteed minimum time, and both vary with temperature and v dd voltage. the watchdog has two additional controls associated with its operation. the nonvolatile enable bit wde allows the /rst to go active if the watchdog reaches the timeout without being restarted. if a reset occurs, the timer will restart on the rising edge of the reset pulse. if wde is not enabled, the watchdog timer still runs but has no effect on /rst. the second control is a nibble that restarts the timer, thus preventing a reset. the timer should be restarted after changing the timeout value. this procedure must be followed to properly load the watchdog registers: address 1. write the starttime value 0bh 2. write the endtime value and wde=1 0ch 3. issue a restart command 0ah the restart command in step 3 must be issued before t dog2 , which was programmed in step 2. the window timer starts counting when the restart command is issued. manual reset the /rst is a bi-directional signal allowing the fm33xx to filter and de-bounce a manual reset switch. the /rst input detects an external low condition and responds by driving the /rst signal low for 100 ms (max.). this effectively filters and de- bounces a reset switch. after this timeout (t rpw ), the user may continue pulling down on the /rst pin, but spi commands will not be locked out. figure 5. manual reset note the internal weak pull-up eliminates the need for additional external components. reset flags in case of a reset condition, a flag bit will be set to indicate the source of the reset. a low-v dd reset is indicated by the por bit, register 09h bit 5. there are two watchdog reset flags - one for an early fault (ewdf) and the other for a late fault (lwdf), located in register 09h bits 7 and 6. a manual reset will result in no flag being set, so the absence of a flag is a manual reset. note that the bits are set in response to reset sources but they must be cleared by the user. it is possible to read the register and have rst watchdog restart start time end time 100 ms (max) window timebase down counter watchdog timer settings 100 ms clock wde /rst wr3-0 = 1010b to restart fm33xx rese t switch rst mcu switch behavior rst fm33xx drives 100 ms (max.) fm33256/fm3316 spi companion w/ fram rev. 2.0 feb. 2009 page 6 of 28 both sources indicated if both have occurred since the user cleared them. power fail comparator an analog comparator compares the pfi input pin to an onboard 1.5v reference. when the pfi input voltage drops below this threshold, the comparator will drive the pfo pin to a low state. the comparator has 100 mv of hysteresis (rising voltage only) to reduce noise sensitivity. the most common application of this comparator is to create an early warning power fail interrupt (nmi). this can be accomplished by connecting the pfi pin to an upstream power supply via a resistor divider. an application circuit is shown below. the comparator is a general purpose device and its application is not limited to the nmi function. figure 6. comparator as a power-fail warning if the power-fail comparator is not used, the pfi pin should be tied to either v dd or v ss . note that the pfo output will drive to v dd or v ss as well. event counter the fm33xx offers the user a nonvolatile 16-bit event counter. the input pin cnt has a programmable edge detector. the cnt pin clocks the counter. the counter is located in registers 0e-0fh. when the programmed edge polarity occurs, the counter will increment its count value. the register value is read by setting the rc bit (register 0dh, bit 3) to 1. this takes a snapshot of the counter byte allowing a stable value even if a count occurs during the read. the register value can be written by first setting the wc bit (register 0dh, bit 2) to 1. the user then may clear or preset the counter by writing to registers 0e-0fh. counts are blocked when the wc bit is set, so the user must clear the bit to allow counts. the counter polarity control bit is cp, register 0dh bit 0. when cp is 0, the counter increments on a falling edge of cnt, and when cp is set to 1, the counter increments on a rising edge of cnt. the polarity bit cp is nonvolatile. figure 7. event counter the counter does not wrap back to zero when it reaches the limit of 65,535 (ffffh). care must be taken prior to the rollover, and a subsequent counter reset operation must occur to continue counting. there is also a control bit that allows the user to define the counter as nonvolatile or battery-backed. the counter is nonvolatile when the nvc bit (register 0dh, bit 7) is logic 1 and battery-backed when the nvc bit is logic 0. setting the counter mode to battery-backed allows counter operation under v bak (as well as v dd ) power. the lowest operating voltage for battery-backed mode is 2.0v. when set to ?nonvolatile? mode, the counter operates only when v dd is applied and is above the v tp voltage. the event counter may be programmed to detect a tamper event, such as the system?s case or access door being opened. a normally closed switch is tied to the cnt pin and the other contact to the case chassis, usually ground. the typical solution uses a pullup resistor on the cnt pin and will continuously draw battery current. the fm33xx chip allows the user to invoke a polled mode, which occasionally samples the pin in order to minimize battery drain. it internally tries to pull the cnt pin up and if open circuit will be pulled up to a v ih level, which will trip the edge detector and increment the event counter value. setting the poll bit (register 0dh, bit 1) places the cnt pin into this mode. this mode allows the event counter to detect a rising edge tamper event but the user is restricted to operating in battery- backed mode (nvc=0) and using rising edge detection (cp=1). the cnt pin is polled once every 125ms. the additional average i bak current is less than 5na. the polling timer circuit operates from the rtc, so the oscillator must be enabled for this to function properly. figure 8. polled mode on cnt pin detects tamper + - 1.5v ref regulator vdd fm33xx to mcu nmi input pfo 16-bit counte r cnt cp cnt fm33xx 125ms < 100pf vbak fm33256/fm3316 spi companion w/ fram rev. 2.0 feb. 2009 page 7 of 28 in the polled mode, the internal pullup circuit can source a limited amount of current. the maximum capacitance (switch open circuit) allowed on the cnt pin is 100pf. serial number a memory location to write a 64-bit serial number is provided. it is a writeable nonvolatile memory block that can be locked by the user once the serial number is set. the 8 bytes of data and the lock bit are all accessed via unique op-codes for the rtc and processor companion registers. therefore the serial number area is separate and distinct from the memory array. the serial number registers can be written an unlimited number of times, so these locations are general purpose memory. however once the lock bit is set, the values cannot be altered and the lock cannot be removed. once locked the serial number registers can still be read by the system. the serial number is located in registers 10h to 17h. the lock bit is snl, register 18h bit 7. setting the snl bit to a 1 disables writes to the serial number registers, and the snl bit cannot be cleared . alarm the alarm function compares user-programmed values to the corresponding time/date values and operates under v dd or v bak power. when a match occurs, an alarm event occurs. the alarm drives an internal flag af (register 00h, bit 6) and may drive the acs pin, if desired, by setting the al/sw bit (register 18h, bit 6) in the companion control register. the alarm condition is cleared by writing a ?0? to the af bit. there are five alarm match fields. they are month, date, hours, minutes, and seconds. each of these fields also has a match bit that is used to determine if the field is used in the alarm match logic. setting the match bit to ?0? indicates that the corresponding field will be used in the match process. depending on the match bits, the alarm can occur as specifically as one particular second on one day of the month, or as frequently as once per second continuously. the msb of each alarm register is a match bit. examples of the match bit settings are shown in table 3. selecting none of the match bits (all ?1?s) indicates that no match is required. the alarm occurs every second. setting the match select bit for seconds to ?0? causes the logic to match the seconds alarm value to the current time of day. since a match will occur for only one value per minute, the alarm occurs once per minute. likewise setting the seconds and minutes match select bits causes an exact match of these values. thus, an alarm will occur once per hour. setting seconds, minutes, and hours causes a match once per day. lastly, selecting all match-values causes an exact time and date match. selecting other bit combinations will not produce meaningful results, however the alarm circuit will follow the functions described. there are two ways a user can detect an alarm event, by reading the af flag or monitoring the acs pin. the interrupt pin on the host processor may be used to detect an alarm event. the af flag in register 00h (bit 6) will indicate that a time/date match has occurred. the af flag will be set to ?1? when a match occurs. the aen bit must be set to enable the af flag on alarm matches. the flag and acs pin will remain in this state until the af bit is cleared by writing it to a ?0?. clearing the aen bit will prevent further matches from setting af but will not automatically clear the af flag. the rtc alarm is integrated into the special function registers and shares its output pin with the 512hz calibration and square wave outputs. when the rtc calibration mode is invoked by setting the cal bit (register 00h, bit 2), the acs output pin will be driven with a 512 hz square wave and the alarm will continue to operate. since most users only invoke the calibration mode during production this should have no impact on the otherwise normal operation of the alarm. the acs output may also be used to drive the system with a frequency other than 512 hz. the al/sw bit (register 18h, bit 6) must be ?0?. a user-selectable frequency is provided by f0 and f1 (register 18h, bits 4 and 5). the other frequencies are 1, 4096, and 32768 hz. if a continuous frequency output is enabled with cal mode, the alarm function will not be available. following is a summary table that shows the relationship between register control settings and the state of the acs pin. table 2. state of register bit function of acs pin cal aen al/sw 0 1 1 /alarm 0 x 0 sq wave out 1 x x 512 hz out 0 0 1 hi-z fm33256/fm3316 spi companion w/ fram rev. 2.0 feb. 2009 page 8 of 28 table 3. alarm match bit examples seconds minutes hours date months alarm condition 1 1 1 1 1 no match required = alarm 1/second 0 1 1 1 1 alarm when seconds match = alarm 1/minute 0 0 1 1 1 alarm when seconds, minutes match = alarm 1/hour 0 0 0 1 1 alarm when seconds, minutes, hours match = alarm 1/date 0 0 0 0 1 alarm when seconds, minutes, hours, date match = alarm 1/month real-time clock operation the real-time clock (rtc) is a timekeeping device that can be capacitor- or battery-backed for permanently-powered operation. it offers a software calibration feature that allows high accuracy. the rtc consists of an oscillator, clock divider, and a register system for user access. it divides down the 32.768 khz time-base and provides a minimum resolution of seconds (1hz). static registers provide the user with read/write access to the time values. it includes registers for seconds, minutes, hours, day- of-the-week, date, months, and years. a block diagram shown in figure 9 illustrates the rtc function. the user registers are synchronized with the timekeeper core using r and w bits in register 00h. the r bit is used to read the time. changing the r bit from 0 to 1 transfers timekeeping information from the core into the user registers 02-08h that can be read by the user. if a timekeeper update is pending when r is set, then the core will be updated prior to loading the user registers. the user registers are frozen and will not be updated again until the r bit is cleared to a ?0?. the w bit is used to write new time/date values. setting the w bit to a ?1? stops the rtc and allows the timekeeping core to be written with new data. clearing it to ?0? causes the rtc to start running based on the new values loaded in the timekeeper core. the rtc may be synchronized to another clock source. on the 8 th clock of the write to register 00h (w=0), the rtc starts counting with a timebase that has been reset to zero milliseconds. note: users should be certain not to load invalid values, such as ffh, to the timekeeping registers. updates to the timekeeping core occur continuously except when locked. figure 9. real-time clock core block diagram 32.768 khz crystal oscillator clock divider update logic 512 hz or sw out w r seconds 7 bits minutes 7 bits hours 6 bits date 6 bits months 5 bits years 8 bits cf days 3 bits user registers 1 hz /oscen fm33256/fm3316 spi companion w/ fram rev. 2.0 feb. 2009 page 9 of 28 backup power the real-time clock and alarm are intended to be permanently powered. when the primary system power fails, the voltage on the vdd pin will drop. when the vdd voltage is less than v sw , the rtc (and event counter) will switch to the backup power supply on vbak. the clock operates at extremely low current in order to maximize battery or capacitor life. however, an advantage of combining a clock function with f-ram memory is that data is not lost regardless of the backup power source. trickle charger to facilitate capacitor backup, the vbak pin can optionally provide a trickle charge current. when the vbc bit (register 18h bit 3) is set to a ?1?, the v bak pin will source approximately 80 a until v bak reaches v dd . this charges the capacitor to v dd without an external diode and resistor charger. there is a fast charge mode which is enabled by the fc bit (register 18h, bit 2). in this mode the trickle charger current is set to approximately 1 ma, allowing a large backup capacitor to charge more quickly. ? in the case where no battery is used, the v bak pin should be tied to v ss and vbc bit cleared. ! ! ! ! note: systems using lithium batteries should clear the vbc bit to 0 to prevent battery charging. the vbak circuitry includes an internal 1 k ? series resistor as a safety element. the trickle charger is ul recognized. calibration when the cal bit in register 00h is set to a ?1?, the clock enters calibration mode. the fm33xx devices employ a digital method for calibrating the crystal oscillator frequency. the digital calibration scheme applies a digital correction to the rtc counters based on the calibration settings, cals and cal.4-0. in calibration mode (cal=1), the acs pin is driven with a 512 hz (nominal) square wave and the alarm is temporarily unavailable. any measured deviation from 512 hz translates into a timekeeping error. the user measures the frequency and writes the appropriate correction value to the calibration register. the correction codes are listed in the table below. for convenience, the table also shows the frequency error in ppm. positive ppm errors require a negative adjustment that removes pulses. negative ppm errors require a positive correction that adds pulses. positive ppm adjustments have the cals (sign) bit set to 1, where as negative ppm adjustments have cals = 0. after calibration, the clock will have a maximum error of 2.17 ppm or 0.09 minutes per month at the calibrated temperature. the user will not be able to see the effect of the calibration setting on the 512 hz output. the addition or subtraction of digital pulses occurs after the 512 hz output. the calibration setting is stored in f-ram so it is not lost should the backup source fail. it is accessed with bits cal.4-0 in register 01h. this value only can be written when the cal bit is set to a 1. to exit the calibration mode, the user must clear the cal bit to a logic 0. when the cal bit is 0, the acs pin will revert to the function according to table 2. crystal type the crystal oscillator is designed to use a 12.5pf crystal without the need for external components, such as loading capacitors. the fm33xx device has built-in loading capacitors that match the crystal. if a 32.768khz crystal is not used, an external oscillator may be connected to the fm33xx. apply the oscillator to the x1 pin. its high and low voltage levels can be driven rail-to-rail or amplitudes as low as approximately 500mv p-p. to ensure proper operation, a dc bias must be applied to the x2 pin. it should be centered between the high and low levels on the x1 pin. this can be accomplished with a voltage divider. figure 10. external oscillator in the example, r1 and r2 are chosen such that the x2 voltage is centered around the oscillator drive levels. if you wish to avoid the dc current, you may choose to drive x1 with an external clock and x2 with an inverted clock using a cmos inverter. layout recommendations the x1 and x2 crystal pins employ very high impedance circuits and the oscillator connected to these pins can be upset by noise or extra loading. to reduce rtc clock errors from signal switching noise, a guard ring should be placed around these pads and the guard ring grounded. high speed spi traces x1 vd d fm33xx r1 r2 x2 fm33256/fm3316 spi companion w/ fram rev. 2.0 feb. 2009 page 10 of 28 should be routed away from the x1/x2 pads. the x1 and x2 trace lengths should be less than 5 mm. the use of a ground plane on the backside or inner board layer is preferred. see layout example. red is the top layer, green is the bottom layer. layout for surface mount crystal layout for through hole crystal (red = top layer, green = bottom layer) (red = top layer, green = bottom layer) table 4. digital calibration adjustments positive calibration for slow clocks: calibration will achieve 2.17 ppm after calibration measured frequency range error range (ppm) min max min max program calibration register to: 0 512.0000 511.9989 0 2.17 000000 1 511.9989 511.9967 2.18 6.51 100001 2 511.9967 511.9944 6.52 10.85 100010 3 511.9944 511.9922 10.86 15.19 100011 4 511.9922 511.9900 15.20 19.53 100100 5 511.9900 511.9878 19.54 23.87 100101 6 511.9878 511.9856 23.88 28.21 100110 7 511.9856 511.9833 28.22 32.55 100111 8 511.9833 511.9811 32.56 36.89 101000 9 511.9811 511.9789 36.90 41.23 101001 10 511.9789 511.9767 41.24 45.57 101010 11 511.9767 511.9744 45.58 49.91 101011 12 511.9744 511.9722 49.92 54.25 101100 13 511.9722 511.9700 54.26 58.59 101101 14 511.9700 511.9678 58.60 62.93 101110 15 511.9678 511.9656 62.94 67.27 101111 16 511.9656 511.9633 67.28 71.61 110000 17 511.9633 511.9611 71.62 75.95 110001 18 511.9611 511.9589 75.96 80.29 110010 19 511.9589 511.9567 80.30 84.63 110011 20 511.9567 511.9544 84.64 88.97 110100 21 511.9544 511.9522 88.98 93.31 110101 22 511.9522 511.9500 93.32 97.65 110110 23 511.9500 511.9478 97.66 101.99 110111 24 511.9478 511.9456 102.00 106.33 111000 25 511.9456 511.9433 106.34 110.67 111001 26 511.9433 511.9411 110.68 115.01 111010 27 511.9411 511.9389 115.02 119.35 111011 28 511.9389 511.9367 119.36 123.69 111100 29 511.9367 511.9344 123.70 128.03 111101 30 511.9344 511.9322 128.04 132.37 111110 31 511.9322 511.9300 132.38 136.71 111111 negative calibration for fast clocks: calibration will achieve 2.17 ppm after calibration measured frequency range error range (ppm) min max min max program calibration register to: /cs so cnt vbak x2 x1 vss /cs so cnt vbak x2 x1 vss fm33256/fm3316 spi companion w/ fram rev. 2.0 feb. 2009 page 11 of 28 0 512.0000 512.0011 0 2.17 000000 1 512.0011 512.0033 2.18 6.51 000001 2 512.0033 512.0056 6.52 10.85 000010 3 512.0056 512.0078 10.86 15.19 000011 4 512.0078 512.0100 15.20 19.53 000100 5 512.0100 512.0122 19.54 23.87 000101 6 512.0122 512.0144 23.88 28.21 000110 7 512.0144 512.0167 28.22 32.55 000111 8 512.0167 512.0189 32.56 36.89 001000 9 512.0189 512.0211 36.90 41.23 001001 10 512.0211 512.0233 41.24 45.57 001010 11 512.0233 512.0256 45.58 49.91 001011 12 512.0256 512.0278 49.92 54.25 001100 13 512.0278 512.0300 54.26 58.59 001101 14 512.0300 512.0322 58.60 62.93 001110 15 512.0322 512.0344 62.94 67.27 001111 16 512.0344 512.0367 67.28 71.61 010000 17 512.0367 512.0389 71.62 75.95 010001 18 512.0389 512.0411 75.96 80.29 010010 19 512.0411 512.0433 80.30 84.63 010011 20 512.0433 512.0456 84.64 88.97 010100 21 512.0456 512.0478 88.98 93.31 010101 22 512.0478 512.0500 93.32 97.65 010110 23 512.0500 512.0522 97.66 101.99 010111 24 512.0522 512.0544 102.00 106.33 011000 25 512.0544 512.0567 106.34 110.67 011001 26 512.0567 512.0589 110.68 115.01 011010 27 512.0589 512.0611 115.02 119.35 011011 28 512.0611 512.0633 119.36 123.69 011100 29 512.0633 512.0656 123.70 128.03 011101 30 512.0656 512.0678 128.04 132.37 011110 31 512.0678 512.0700 132.38 136.71 011111 fm33256/fm3316 spi companion w/ fram rev. 2.0 feb. 2009 page 12 of 28 register map the rtc and processor companion functions are accessed via 30 special function registers, which are mapped to unique op-codes. the interface protocol is described on page 17. the registers contain timekeeping data, alarm settings, control bits, and information flags. a description of each register follows the summary table. register map summary table battery-backed = nonvolatile = bb/nv user programmable = address d7 d6 d5 d4 d3 d2 d1 d0 function range /match 0 0 10 mo alarm months alarm month 01-12 /match 0 10 date alarm date alarm date 01-31 /match 0 alarm 10 hours alarm hours alarm hours 00-23 /match alarm 10 minutes alarm minutes alarm minutes 00-59 /match alarm 10 seconds alarm seconds alarm seconds 00-59 snl al/sw f1 f0 vbc fc vtp1 vtp0 companion control serial number 7 ffh serial number 6 ffh serial number 5 ffh serial number 4 ffh serial number 3 ffh serial number 2 ffh serial number 1 ffh serial number 0 ffh event counter byte 1 event counter 1 ffh event counter byte 0 event counter 0 ffh nvc - - - rc wc poll cp event counter control 0ch wde - - wdset4 wdet3 wdet2 wdet1 wdet0 watchdog control 0bh - - - wdst4 wdst3 wdst2 wdst1 wdst0 watchdog control 0ah ----wr3wr2wr1wr0watchdog restart 09hewdflwdfporlb----watchdog flags 08h 10 years years years 00-99 07h 00010 mo months month 01-12 06h 00 10 date date date 01-31 05h 00000 day 01-07 04h 00 10 hours hours hours 00-23 03h 0 10 minutes minutes minutes 00-59 02h 0 10 seconds seconds seconds 00-59 01h - - cals cal4 cal3 cal2 cal1 cal0 cal/control 00h /oscen af cf aen reserved cal w r rtc/alarm control 0eh serial number byte 1 serial number byte 0 1ah 19h 10h 1dh 1ch 1bh day serial number byte 7 serial number byte 6 serial number byte 5 serial number byte 4 serial number byte 3 serial number byte 2 0dh 0fh 18h 16h 17h 11h 13h 14h 15h 12h note: when the device is first powered up and programmed, all timekeeping registers must be written because the battery- backed register values cannot be guaranteed. the table below shows the default values of the non-volatile registers and some o f the battery-backed bits. all other register values should be treated as unknown . default register values address hex value address hex value 1dh 0x81 12h 0x00 1ch 0x81 11h 0x00 1bh 0x80 10h 0x00 1ah 0x80 0fh 0x00 19h 0x80 0eh 0x00 18h 0x40 0dh 0x01 17h 0x00 0ch 0x00 16h 0x00 0bh 0x00 15h 0x00 01h 0x00 14h 0x00 00h 0x80 13h 0x00 fm33256/fm3316 spi companion w/ fram rev. 2.0 feb. 2009 page 13 of 28 register description address description 1dh alarm ? month d7 d6 d5 d4 d3 d2 d1 d0 m 0 0 10 month month.3 month.2 month.1 month.0 contains the alarm value for the month and the mask bit to select or deselect the month value. /m match. setting this bit to 0 causes the month value to be used in the alarm match logic. setting this bit to 1 causes the match circuit to ignore the month value. battery-backed, read/write. 1ch alarm ? date d7 d6 d5 d4 d3 d2 d1 d0 m 0 10 date.1 10 date.0 date.3 date.2 date.1 date.0 contains the alarm value for the date and the mask bit to select or deselect the date value. /m match: setting this bit to 0 causes the date value to be used in the alarm match logic. setting this bit to 1 causes the match circuit to ignore the date value. battery-backed, read/write. 1bh alarm ? hours d7 d6 d5 d4 d3 d2 d1 d0 m 0 10 hours.1 10 hours.0 hours.3 hours2 hours.1 hours.0 contains the alarm value for the hours and the mask bit to select or deselect the hours value. /m match: setting this bit to 0 causes the hours value to be used in the alarm match logic. setting this bit to 1 causes the match circuit to ignore the hours value. battery-backed, read/write. 1ah alarm ? minutes d7 d6 d5 d4 d3 d2 d1 d0 m 10 min.2 10 min.1 10 min.0 min.3 min.2 min.1 min.0 contains the alarm value for the minutes and the mask bit to select or deselect the minutes value /m match: setting this bit to 0 causes the minutes value to be used in the alarm match logic. setting this bit to 1 causes the match circuit to ignore the minutes value. battery-backed, read/write. 19h alarm ? seconds d7 d6 d5 d4 d3 d2 d1 d0 m 10 sec.2 10 sec.1 10 sec.0 seconds.3 seconds.2 seconds.1 seconds.0 contains the alarm value for the seconds and the mask bit to select or deselect the seconds value. /m match: setting this bit to 0 causes the seconds value to be used in the alarm match logic. setting this bit to 1 causes the match circuit to ignore the seconds value. battery-backed, read/write. 18h companion control d7 d6 d5 d4 d3 d2 d1 d0 snl al/sw f1 f0 vbc fc vtp1 vtp0 snl serial number lock: setting to a ?1? makes registers 10h to 17h and snl read-only. snl cannot be cleared once set to ?1?. nonvolatile, read/write. al/sw alarm/square wave select: when set to ?1?, the alarm match drives the acs pin as well as the af flag. when set to ?0?, the selected square wave freq will be driven on the acs pin, and an alarm match only sets the af flag. nonvolatile, read/write. f(1:0) square wave freq select: these bits select the frequency on the acs pin when the cal and al/sw bits are both ?0?. nonvolatile. setting f(1:0) setting f(1:0) 1 hz 00 (default) 4096 hz 10 5 12 hz 01 32768 hz 11 vbc vbak charger control: setting vbc to ?1? (and fc=0) causes a 80 a (1 ma if fc=1) trickle charge current to be supplied on v ba k . clearing vbc to ?0? disables the charge current. battery-backed, read/write. fc fast charge: setting fc to ?1? (and vbc=1) causes a ~1 ma trickle charge current to be supplied on v bak . clearing vbc to ?0? disables the charge current. battery-backed, read/write. vtp(1:0) vtp select. these bits control the reset trip point for the low-v dd reset function. when v dd is below the selected v tp voltage, the reset pin /rst will drive low and the spi interface will be locked out. nonvolatile, read/write. fm33256/fm3316 spi companion w/ fram rev. 2.0 feb. 2009 page 14 of 28 setting vtp(1:0) 2.60v 00 (factory default) 2.75v 01 2.9v 10 3.0v 11 17h serial number byte 7 d7 d6 d5 d4 d3 d2 d1 d0 sn.63 sn.62 sn.61 sn.60 sn.59 sn.58 sn.57 sn.56 16h serial number byte 6 d7 d6 d5 d4 d3 d2 d1 d0 sn.55 sn.54 sn.53 sn.52 sn.51 sn.50 sn.49 sn.48 15h serial number byte 5 d7 d6 d5 d4 d3 d2 d1 d0 sn.47 sn.46 sn.45 sn.44 sn.43 sn.42 sn.41 sn.40 14h serial number byte 4 d7 d6 d5 d4 d3 d2 d1 d0 sn.39 sn.38 sn.37 sn.36 sn.35 sn.34 sn.33 sn.32 13h serial number byte 3 d7 d6 d5 d4 d3 d2 d1 d0 sn.31 sn.30 sn.29 sn.28 sn.27 sn.26 sn.25 sn.24 12h serial number byte 2 d7 d6 d5 d4 d3 d2 d1 d0 sn.23 sn.22 sn.21 sn.20 sn.19 sn.18 sn.17 sn.16 11h serial number byte 1 d7 d6 d5 d4 d3 d2 d1 d0 sn.15 sn.14 sn.13 sn.12 sn.11 sn.10 sn.9 sn.8 10h serial number byte 0 d7 d6 d5 d4 d3 d2 d1 d0 sn.7 sn.6 sn.5 sn.4 sn.3 sn.2 sn.1 sn.0 all serial number bytes are read/write when snl=0, read-only when snl=1. nonvolatile. 0fh event counter byte 1 d7 d6 d5 d4 d3 d2 d1 d0 ec.15 ec.14 ec.13 ec.12 ec.11 ec.10 ec.9 ec.8 event counter byte 1. increments on programmed edge event on cnt input. nonvolatile when nvc=1, battery-backed when nvc=0, read/write. 0eh event counter byte 0 d7 d6 d5 d4 d3 d2 d1 d0 ec.7 ec.6 ec.5 ec.4 ec.3 ec.2 ec.1 ec.0 event counter byte 0. increments on programmed edge event on cnt input. nonvolatile when nvc=1, battery-backed when nvc=0, read/write. 0dh event counter control d7 d6 d5 d4 d3 d2 d1 d0 nvc - - - rc wc poll cp nvc nonvolatile/volatile counter: setting this bit to 1 makes the counter nonvolatile and counter operates only when v dd is greater than v tp . setting this bit to 0 makes the counter volatile, which allows counter operation under v ba k or v dd power. nonvolatile, read/write. rc read counter. setting this bit to 1 takes a snapshot of the two counter bytes allowing the system to read the values without missing count events. the rc bit will be automatically cleared. wc write counter. setting this bit to a 1 allows the user to write the counter bytes. while wc=1, the counter is blocked from count events on the cnt pin. the wc bit must be cleared by the user to activate the counter. poll polled mode: when poll=1, the cnt pin is sampled for 30s every 125ms. if poll is set, the nvc bit is internally cleared and the cp bit is set to detect a rising edge. the rtc oscillator must be enabled (/oscen=0) fm33256/fm3316 spi companion w/ fram rev. 2.0 feb. 2009 page 15 of 28 to operate in polled mode. when poll=0, cnt pin is continuously active. nonvolatile, read/write. cp the cnt pin detects falling edges when cp = 0, rising edges when cp = 1. nonvolatile, read/write. 0ch watchdog control d7 d6 d5 d4 d3 d2 d1 d0 wde - - wdet4 wdet3 wdet2 wdet1 wdet0 wde watchdog enable: when wde=1, a watchdog timer fault will cause the /rst signal to go active. when wde = 0 the timer runs but has no effect on the /rst pin. nonvolatile, read/write. wdet(4:0) watchdog endtime: sets the ending time for the watchdog window timer with 60 ms (min.) resolution. the window timer allow independent leading and trailing edges (start and end of window) to be set. new watchdog timeouts are loaded when the timer is restarted by writing the 1010b pattern to wr(3:0). to save power (disable timer circuit), the endtime may be set to all zeroes. nonvolatile, read/write. watchdog endtime wdet4 wdet3 wdet2 wdet1 wdet0 disables timer 0 0 0 0 0 (min.) (max.) 60 ms 200 ms 0 0 0 0 1 120 ms 400 ms 0 0 0 1 0 180 ms 600 ms 0 0 0 1 1 . . . . . . 1200 ms 4000 ms 1 0 1 0 0 1260 ms 4200 ms 1 0 1 0 1 1320 ms 4400 ms 1 0 1 1 0 . . . . . . 1740 ms 5800 ms 1 1 1 0 1 1800 ms 6000 ms 1 1 1 1 0 1860 ms 6200 ms 1 1 1 1 1 0bh watchdog control d7 d6 d5 d4 d3 d2 d1 d0 - - - wdst4 wdst3 wdst2 wdst1 wdst0 wdst(4:0) watchdog starttime. sets the starting time for the watchdog window timer with 25 ms (max.) resolution. the window timer allow independent leading and trailing edges (start and end of window) to be set. new watchdog timer settings are loaded when the timer is restarted by writing the 1010b pattern to wr(3:0). nonvolatile, read/write. watchdog starttime wdst4 wdst3 wdst2 wdst1 wdst0 0 ms (default) 0 0 0 0 0 (min.) (max.) 7.5 ms 25 ms 0 0 0 0 1 15.0 ms 50 ms 0 0 0 1 0 22.5 ms 75 ms 0 0 0 1 1 . . . . . . 150 ms 500 ms 1 0 1 0 0 157.5 ms 525 ms 1 0 1 0 1 165 ms 550 ms 1 0 1 1 0 . . . . . . 217.5 ms 725 ms 1 1 1 0 1 225 ms 750 ms 1 1 1 1 0 232.5 ms 775 ms 1 1 1 1 1 0ah watchdog restart d7 d6 d5 d4 d3 d2 d1 d0 - - - - wr3 wr2 wr1 wr0 wr(3:0) watchdog restart. writing a pattern 1010b to wr(3:0) restarts the watchdog timer. the upper nibble contents do not affect this operation. writing any pattern other than 1010b to wr3-0 has no effect on the watchdog. write-only. fm33256/fm3316 spi companion w/ fram rev. 2.0 feb. 2009 page 16 of 28 09h watchdog flags d7 d6 d5 d4 d3 d2 d1 d0 ewdf lwdf por lb - - - - ewdf early watchdog timer fault flag: when a watchdog restart occurs too early (before the programmed watchdog starttime), the /rst pin is driven low and this flag is set. it must be cleared by the user. note that both ewdf and por could be set if both reset sources have occurred since the flags were cleared by the user. battery- backed, read/write. lwdf late watchdog timer fault flag: when either a watchdog restart occurs too late (after the progr ammed watchdog endtime) or no restart occurs, the /rst pin is driven low and this flag is set. it must be cleared by the user. note that both lwdf and por could be set if both reset sources have occurred since the flags were cleared by the user. battery-backed, read/write. por power-on reset: when the /rst signal is activated by v dd < v tp , the por bit will be set to 1. a manual reset will not set this flag. note that one or both of the watchdog flags and the por flag could be set if both reset sources have occurred since the flags were cleared by the user. battery-backed, read/write. (internally set, user must clear bit) lb low backup: if the v bak source drops to a voltage level insufficient to operate the rtc/alarm when v dd fm33256/fm3316 spi companion w/ fram rev. 2.0 feb. 2009 page 18 of 28 serial peripheral interface ? spi bus the fm33xx employs a serial peripheral interface (spi) bus. it is specified to operate at speeds up to 16 mhz. this high-speed serial bus provides high performance serial communication to a host microcontroller. many common microcontrollers have hardware spi ports allowing a direct interface. it is quite simple to emulate the port using ordinary port pins for microcontrollers that do not. the fm33xx devices operate in spi mode 0 and 3. the spi interface uses a total of four pins: clock, data-in, data-out, and chip select. a typical system configuration uses an fm33xx and a standalone spi device with a microcontroller that has a dedicated spi port, as figure 10 illustrates. note that the clock, data-in, and data-out pins are common among all devices. the /cs pins must be driven separately for the fm33xx and each additional spi device. figure 10. system configuration with spi port for a microcontroller that has no dedicated spi bus, a general purpose port may be used. to reduce hardware resources on the controller, it is possible to connect the two data pins together. figure 11 shows a configuration that uses only three pins. microcontroller fm33xx so si sck cs figure 11. system configuration without spi port protocol overview the spi interface is a synchronous serial interface using clock and data pins. it is intended to support multiple devices on the bus. each device is activated using a chip select. once chip select is activated by the bus master, the fm33xx will begin monitoring the clock and data lines. the relationship between the falling edge of /cs, the clock and data is dictated by the spi mode. the device will make a determination of the spi mode on the falling edge of each chip select. while there are four such modes, the fm33xx supports only modes 0 and 3. figure 12 shows the required signal relationships for modes 0 and 3. for both modes, data is clocked into the fm33xx on the rising edge of sck and data is expected on the first rising edge after /cs goes active. if the clock starts from a high state, it will fall prior to the first data transfer in order to create the first rising edge. spi mode 0: cpol=0, cpha=0 spi mode 3: cpol=1, cpha=1 figure 12. spi modes 0 & 3 the spi protocol is controlled by op-codes. these op-codes specify the commands to the device. after /cs is activated the first byte transferred from the bus master is the op-code. following the op-code, any addresses and data are then transferred. note that the wren and wrdi op-codes are commands with no subsequent data transfer. important: the /cs pin must go inactive after an operation is complete and before a new op-code can be issued. there is only one valid op-code per active chip select. data transfer all data transfers to and from the fm33xx occur in 8-bit groups. they are synchronized to the clock signal (sck), and they transfer most significant bit (msb) first. serial inputs are registered on the rising edge of sck. outputs are driven from the falling edge of sck. fm33256/fm3316 spi companion w/ fram rev. 2.0 feb. 2009 page 19 of 28 command structure there are eight commands called op-codes that can be issued by the bus master to the fm33xx. they are listed in the table below. these op-codes control the functions performed by the memory and processor companion. they can be divided into three categories. first, there are commands that have no subsequent operations. they perform a single function, such as, enabling a write operation. second are commands followed by one data byte, either in or out. they operate on the status register. the third group includes commands for memory and processor companion transactions followed by address and one or more bytes of data. table 4. op-code commands name description op-code wren set write enable latch 0000 0110b wrdi write disable 0000 0100b rdsr read status register 0000 0101b wrsr write status register 0000 0001b read read memory data 0000 0011b write write memory data 0000 0010b rdpc read proc. companion 0001 0011b wrpc write proc. companion 0001 0010b wren ? set write enable latch the fm33xx will power up with writes disabled. the wren command must be issued prior to any write operation. sending the wren op-code will allow the user to issue subsequent op-codes for write operations. these include writing the status register, writing the processor companion, and writing the memory. sending the wren op-code causes the internal write enable latch to be set. a flag bit in the status register, called wel, indicates the state of the latch. wel=1 indicates that writes are permitted. attempting to write the wel bit in the status register has no effect on the state of this bit. the wel bit will automatically be cleared on the rising edge of /cs following a wrdi, wrsr, wrpc, or write op-code. no other op-code affects the state of the wel bit. this prevents further writes to the status register, f-ram memory, or the companion register space without another wren command. figure 13 below illustrates the wren command bus configuration. wrdi ? write disable the wrdi command disables all write activity by clearing the write enable latch. the user can verify that writes are disabled by reading the wel bit in the status register and verifying that wel=0. figure 14 illustrates the wrdi command bus configuration. hi-z 0 1 2 3 4 5 6 7 0 0 0 0 0 1 1 0 cs sck si so figure 13. wren bus configuration cs sck si so hi-z 0 1 2 3 4 5 6 7 0 0 0 0 0 1 0 0 figure 14. wrdi bus configuration fm33256/fm3316 spi companion w/ fram rev. 2.0 feb. 2009 page 20 of 28 rdsr ? read status register the rdsr command allows the bus master to verify the contents of the status register. reading this register provides information about the current state of the write protection bits. following the rdsr op- code, the fm33xx will return one byte with the contents of the status register. the status register is described in detail in a later section. wrsr ? write status register the wrsr command allows the user to select certain write protection features by writing a byte to the status register. prior to sending the wrsr command, the user must send a wren command to enable writes. note that executing a wrsr command is a write operation and therefore clears the write enable latch. the bus timings of rdsr and wrsr are shown below. figure 15. rdsr bus configuration figure 16. wrsr bus configuration rdpc ? read processor companion the rdpc command allows the bus master to verify the contents of the processor companion registers. following the rdpc op-code, a single-byte register address is sent. the fm33xx will then return one or more bytes with the contents of the companion registers. when reading multiple data bytes, the internal register address will wrap around to 00h after 1dh is reached. wrpc ? write processor companion the wrpc command is used to set companion control settings. a wren command is required prior to sending the wrpc command. following the wrpc op-code, a single-byte register address is sent. the controller then drives one or more bytes to program the companion registers. when writing multiple data bytes, the internal register address will wrap around to 00h after 1dh is reached. the rising edge of /cs terminates a wrpc operation. see figure 18. figure 17. processor companion read 01234567012345 01234567 o p-c ode 0 0 0 1 0 0 1 1 msb register address 7 6 5 4 3 2 cs sc k si so 1 6 0 7 lsb msb lsb data out 0 7 hi-z 7 6 5 4 3 21 0 lsb fm33256/fm3316 spi companion w/ fram rev. 2.0 feb. 2009 page 21 of 28 figure 18. processor companion write status register & write protection the write protection features of the fm33xx are multi-tiered. to write the memory, a wren op-code must first be issued, followed by a write op-code. a status register associated with the memory has a write enable latch bit (wel) that is internally set when wren is issued. writes to certain memory blocks are controlled by the block protect bits in the status register. the bp bits may be changed by using the wrsr command. the status register is organized as follows. table 5. status register bit 7 6 5 4 3 2 1 0 name 0 1 0 0 bp1 bp0 wel 0 bits 7, 5, 4, and 0 are fixed at 0, bit 6 is fixed at 1, and none of these bits can be modified. note that bit 0 (ready in eeproms) is unnecessary as the f- ram writes in real-time and is never busy. the bp1 and bp0 control software write-protection features. they are nonvolatile (shaded yellow). the wel flag indicates the state of the write enable latch. attempting to directly write the wel bit in the status register has no effect on its state, since this bit is internally set and cleared via the wren and wrdi commands, respectively. bp1 and bp0 are memory block write protection bits. they specify portions of memory that are write-protected as shown in the following table. table 6. block memory write protection bp1 bp0 protected address range 0 0 none 0 1 upper ? 1 0 upper ? 1 1 all the bp1 and bp0 bits and the write enable latch are the only mechanisms that protect the memory from writes. memory operation the spi interface, which is capable of a relatively high clock frequency, highlights the fast write capability of the f-ram technology. unlike spi-bus eeproms, the fm33xx can perform sequential writes at bus speed. no page register is needed and any number of sequential writes may be performed. write operation all writes to the memory begin with a wren op- code with /cs being asserted and deasserted. the next op-code is a write. the write op-code is followed by a two-byte address value. table 7 shows the addressing scheme for each density. this is the starting address of the first data byte of the write operation. subsequent bytes are data bytes, which are written sequentially. addresses are incremented internally as long as the bus master continues to issue clocks and keeps /cs low. a write operation will be terminated when a write-protected address is directly accessed or when the device has internally incremented the address into a write-protected space. if the last address is reached (e.g. 7fffh on the fm33256), the counter will roll over to 0000h. data is written msb first. the rising edge of /cs terminates a write operation. a write operation is shown in figure 19. note: although the wren op- code is not shown in the timing diagram, it is required prior to sending the write command. eeproms use page buffers to increase their write throughput. this compensates for the technology?s inherently slow write operations. f-ram memories do not have page buffers because each byte is written to the f-ram array immediately after it is clocked in (after the 8 th clock). this allows any number of bytes to be written without page buffer delays. read operation after the falling edge of /cs, the bus master can issue a read op-code. following the read command is a two-byte address value. table 7 shows the addressing scheme for each density. this is the starting address of the first byte of the read operation. 01234567012345 01234567 op-c ode 0 0 0 1 0 0 1 0 msb register address 7 6 5 4 3 2 cs sck si so 1 6 0 7 lsb msb lsb data 7 6 5 4 3 21 0 0 7 hi-z lsb fm33256/fm3316 spi companion w/ fram rev. 2.0 feb. 2009 page 22 of 28 after the op-code and address are issued, the device drives out the read data on the next 8 clocks. the si input is ignored during read data bytes. subsequent bytes are data bytes, which are read out sequentially. addresses are incremented internally as long as the bus master continues to issue clocks and /cs is low. if the last address is reached (e.g. 7fffh on the fm33256), the counter will roll over to 0000h. data is read msb first. the rising edge of /cs terminates a read operation. a read operation is shown in figure 20. cs sck si so 01234567 00 hi-z 1 msb lsb 01234 67 x 0 op-code 16-bit address 0 0 1 11 12 13 14 01234567 7 data in 0 1 2 3 4 5 6 msb lsb 7 0 000 figure 19. memory write cs sck si so 01234567 00 hi-z 1 msb lsb 01234 67 x 0 op-code 16-bit address 0 1 11 12 13 14 01234567 7 data out 0 1 2 3 4 5 6 msb lsb 7 0 1 000 figure 20. memory read addressing f-ram array in the fm33xx family the fm33xx devices include 256kb and 16kb memory densities. the following 2-byte address field is shown for each density. table 7. two-byte memory address part # 1 s t address byte 2 n d address byte fm33256 x a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 fm3316 x x x x x a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 fm33256/fm3316 spi companion w/ fram rev. 2.0 feb. 2009 page 23 of 28 electrical specifications absolute maximum ratings symbol description ratings v dd power supply voltage with respect to v ss -1.0v to +5.0v v in voltage on any signal pin with respect to v ss -1.0v to +5.0v and v in < v dd +1.0v v bak backup supply voltage -1.0v to +4.5v t stg storage temperature -55 c to + 125 c t lead lead temperature (soldering, 10 seconds) 300 c v esd electrostatic discharge voltage - human body model (jedec std jesd22-a114-e) - charged device model (jedec std jesd22-c101-c) - machine model (jedec std jesd22-a115-a) 4kv 750v 200v package moisture sensitivity level msl-1 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this specification is not implied. exposure to absolute maximum ratings conditions for extended periods may affect device reliabilit y. dc operating conditions ( t a = -40 c to + 85 c, v dd = 2.7v to 3.6v unless otherwise specified) symbol parameter min typ max units notes v dd main power supply 2.7 - 3.6 v 1 i dd v dd supply current (vbc=0) @ sck = 1.0 mhz @ sck = 16.0 mhz 1.1 16.0 ma ma 2 i sb standby current trickle charger off (vbc=0) 50 a 3 v bak rtc backup voltage 2.0 3.0 3.6 v 4 i bak rtc backup current 1 a a 6 i qtc v dd quiescent current (vbc=1) 70 1 1 fm33256/fm3316 spi companion w/ fram rev. 2.0 feb. 2009 page 24 of 28 dc operating conditions, continued (t a = -40 c to + 85 c, v dd = 2.7v to 3.6v unless otherwise specified) symbol parameter min typ max units notes v ol output low voltage @ i ol = 3 ma - 0.4 v v oh output high voltage (so, pfo) @ i oh = -2 ma v dd ? 0.8 - v r rst pull-up resistance for /rst inactive 50 400 k ? v pfi power fail input reference voltage 1.475 1.50 1.525 v v hys power fail input (pfi) hysteresis (rising) - 100 mv notes 1. full complete operation. supervisory circuits, rtc, etc operate to lower voltages as specified. 2. sck toggling between v dd -0.3v and v ss , other inputs v ss or v dd -0.3v. 3. all inputs at v ss or v dd, static. trickle charger off (vbc=0). 4. the vbak trickle charger automatically regulates the maximum voltage on this pin for capacitor backup applications. 5. v bak = 3.0v, v dd < v sw , oscillator running, cnt at vbak. 6. v bak will source current when trickle charge is enabled (vbc bit=1), v dd > v bak , and v bak < v bak max. 7. this is the v dd supply current contributed by enabling the trickle charger circuit, and does not account for i baktc . 8. this is the v dd supply current contributed by enabling the watchdog circuit, wde=1 and wdet set to a non-zero value. 9. /rst is asserted active when v dd < v tp . 10. the minimum v dd to guarantee the level of /rst remains a valid v ol level. 11. v in or v out = v ss to v dd . does not apply to pfi, x1, or x2. 12. includes /rst input detection of external reset condition to trigger driving of /rst signal by fm33xx. ac parameters (t a = -40 c to + 85 c, v dd = 2.7v to 3.6v c l = 30 pf) symbol parameter min max units notes f ck sck clock frequency 0 16 mhz t ch clock high time 28 ns 1 t cl clock low time 28 ns 1 t csu chip select setup 10 ns t csh chip select hold 10 ns t od output disable time 20 ns 2 t odv output data valid time 24 ns t oh output hold time 0 ns t d deselect time 90 ns t r data in rise time 50 ns 1,3 t f data in fall time 50 ns 1,3 t su data setup time 6 ns t h data hold time 6 ns notes 1. t ch + t cl = 1/f ck . 2. this parameter is characterized but not 100% tested. 3. rise and fall times measured between 10% and 90% of waveform. supervisor timing (t a = -40 c to + 85 c, v dd = 2.7v to 3.6v) symbol parameter min max units notes t rpw /rst pulse width (active low time) 30 100 ms t rnr /rst response time to v dd fm33256/fm3316 spi companion w/ fram rev. 2.0 feb. 2009 page 26 of 28 /rst timing vdd vtp vrst rst t rpu t vf t rnr t vr fm33256/fm3316 spi companion w/ fram rev. 2.0 feb. 2009 page 27 of 28 mechanical drawing 14-pin soic (jedec standard ms-012 variation ab) all dimensions in millimeters . conversions to inches are not exact. soic package marking scheme legend: xxxx= part number, p= package type (-g) lllllll= lot code ric=ramtron int?l corp, yy=year, ww=work week example: fm33256, ?green? soic package, year 2006, work week 14 fm33256-g1 a70012g ric 0714 xxxxxxx-p lllllll ric yyww fm33256/fm3316 spi companion w/ fram rev. 2.0 feb. 2009 page 28 of 28 revision history revision date summary 1.0 12/18/2006 initial release. 1.1 12/12/2007 changed i qwd and i baktc spec limits. added text that event counter does not roll over. added suggestion to clear vbc bit when vbak is not used. added esd and package msl ratings. 2.0 2/9/2009 changed status to pre-production. added tape and reel ordering information. expanded data retention ratings. added ul recognition of trickle charger. |
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